Hjem

Preface ix To Students About To Study Digital Design ix To Instructors of Digital Design ix How to Use This Book xii RTL-Focused Approach xii Traditional Approach with Some Reordering xii Traditional Approach xiii Acknowledgements xiii About the Cover xiv About the Author xiv Reviewers and Evaluators xv
CHAPTER 1 Introduction 1
1.1 Digital Systems in the World Around Us 1
1.2 The World of Digital Systems 4 Digital versus Analog 4 Digital Encodings and Binary Numbers--0s and 1s 9
1.3 Implementing Digital Systems: Microprocessors versus Digital Circuits 22 Software on Microprocessors: The Digital Workhorse 22 Digital Design--When Microprocessors Aren''t Good Enough 26
1.4 About this Book 28
1.5 Exercises 29
CHAPTER 2 Combinational Logic Design 35
2.1 Introduction 35
2.2 Switches 36 Electronics 101 36 The Amazing Shrinking Switch 37
2.3 The CMOS Transistor 40
2.4 Boolean Logic Gates--Building Blocks for Digital Circuits 43 Boolean Algebra and its Relation to Digital Circuits 43 AND, OR, & NOT Gates 46 Building Simple Circuits Using Gates 49
2.5 Boolean Algebra 52 Notation and Terminology 53 Some Properties of Boolean Algebra 55 Complementing a Function 60
2.6 Representations of Boolean Functions 61 Equations 62 Circuits 62 Truth Tables 62 Converting among Boolean Function Representations 64 Standard Representation and Canonical Form 68 Multiple-Output Combinational Circuits 71
2.7 Combinational Logic Design Process 73
2.8 More Gates 80 NAND & NOR 80 XOR & XNOR 81 Interesting Uses of these Additional Gates 82 Completeness of NAND and of NOR 82 Number of Possible Logic Gates 83
2.9 Decoders and Muxes 84 Decoders 84 Multiplexers (Muxes) 86
2.10 Additional Considerations 91 Nonideal Gate Behavior--Delay 91 Active Low Inputs 92 Demultiplexers and Encoders 93 Schematic Capture and Simulation 93
2.11 Combinational Logic Optimizations and Tradeoffs (See Section
6.2) 95
2.12 Combinational Logic Description Using Hardware Description Languages (See Section
9.2) 95
2.13
Chapter Summary 96
2.14 Exercises 96
CHAPTER 3 Sequential Logic Design: Controllers 105
3.1 Introduction 105
3.2 Storing One Bit--Flip-Flops 106 Feedback--The Basic Storage Method 106 Basic SR Latch 107 Level -Sensitive SR Latch 111 Level-Sensitive D Latch--A Basic Bit Store 112 Edge-Triggered D Flip-Flop--A Robust Bit Store 113 Clocks and Synchronous Circuits 117 Basic Register--Storing Multiple Bits 120
3.3 Finite-State Machines (FSMs) 122 Mathematical Formalism for Sequential Behavior--FSMs 124 How to Capture Desired System Behavior as an FSM 129
3.4 Controller Design 132 Standard Controller Architecture for Implementing an FSM as a Sequential Circuit 132 Controller (Sequential Logic) Design Process 133 Converting a Circuit to an FSM (Reverse Engineering) 140 Common Mistakes when Capturing FSMs 142 FSM and Controller Conventions 145
3.5 More on Flip-Flops and Controllers 146 Non-Ideal Flip-Flop Behavior 146 Flip-Flop Reset and Set Inputs 149 Initial State of a Controller 150 Non-Ideal Controller Behavior: Output Glitches 151
3.6 Sequential Logic Optimizations and Tradeoffs (See Section
6.3) 153
3.7 Sequential Logic Description Using Hardware Description Languages (See Section
9.3) 153
3.8 Product Profile--Pacemaker 153
3.9
Chapter Summary 156
3.10 Exercises 157
CHAPTER 4 Datapath Components 167
4.1 Introduction 167
4.2 Registers 168 Parallel-Load Register 168 Shift Register 173 Multifunction Registers 175 Register Design Process 179
4.3 Adders 181 Adder--Carry-Ripple Style 183
4.4 Comparators 191 Equality (Identity) Comparator 191 Magnitude Comparator--Carry-Ripple Style 192
4.5 Multiplier--Array-Style 195
4.6 Subtractors and Signed Numbers 196 Subtractor for Positive Numbers Only 196 Representing Negative Numbers: Two''s Complement Representation 200 Building a Subtractor Using an Adder and Two''s Complement 203 Detecting Overflow 205
4.7 Arithmetic-Logic Units--ALUs 207
4.8 Shifters 210 Simple Shifters 211 Barrel Shifter 214
4.9 Counters and Timers 215 Up-Counter 216 Up/Down-Counter 217 Counter with Load 218 Timers 222
4.10 Register Files 225
4.11 Datapath Component Tradeoffs (See Section
6.4) 230
4.12 Datapath Component Description Using Hardware Description Languages (See Section
9.4) 230
4.13 Product Profile: An Ultrasound Machine 230 Functional Overview 231 Digital Circuits in an Ultrasound Machine''s Beamformer 234 Future Challenges in Ultrasound 237
4.14
Chapter Summary 237
4.15 Exercises 238
CHAPTER 5 Register-Transfer Level (RTL) Design 247
5.1 Introduction 247
5.2 High-Level State Machines 248
5.3 RTL Design Process 255 Step 2A--Creating a Datapath using Components from a Library 259 Step 2B--Connecting the Datapath to a Controller 262 Step 2C--Deriving the Controller''s FSM 263
5.4 More RTL Design 264 Additional Datapath Components for the Library 264 RTL Design Involving Register Files or Memories 265 RTL Design Pitfall Involving Storage Updates 271 RTL Design Involving a Timer 272 A Data-Dominated RTL Design Example 275
5.5 Determining Clock Frequency 278
5.6 Behavioral-Level Design: C to Gates (Optional) 281
5.7 Memory Components 285 Random Access Memory (RAM) 286 Bit Storage in a RAM 288 Using a RAM 290 Read-Only Memory (ROM) 292 ROM Types 294 Using a ROM 297 The Blurring of the Distinction between RAM and ROM 299
5.8 Queues (FIFOs) 299
5.9 Multiple Processors 303
5.10 Hierarchy--A Key Design Concept 305 Managing Complexity 305 Abstraction 306 Composing a Larger Component from Smaller Versions of the Same Component 307
5.11 RTL Design Optimizations and Tradeoffs (See Section
6.5) 309
5.12 RTL Design Using Hardware Description Languages (See Section
9.5) 310
5.13 Product Profile: Cell Phone 310 Cells and Basestations 310 How Cellular Phone Calls Work 311 Inside a Cell Phone 312
5.14
Chapter Summary 316
5.15 Exercises 317
CHAPTER 6 Optimizations and Tradeoffs 325
6.1 Introduction 325
6.2 Combinational Logic Optimizations and Tradeoffs 327 Two-Level Size Optimization Using Algebraic Methods 327 A Visual Method for Two-Level Size Optimization--K-Maps 329 Don''t Care Input Combinations 336 Automating Two-Level Logic Size Optimization 339 Multilevel Logic Optimization--Performance and Size Tradeoffs 348
6.3 Sequential Logic Optimizations and Tradeoffs 351 State Reduction 351 State Encoding 354 Moore versus Mealy FSMs 360
6.4 Datapath Component Tradeoffs 365 Faster Adders 365 Smaller Multiplier--Sequential (Shift-and-Add) Style 375
6.5 RTL Design Optimizations and Tradeoffs 377 Pipelining 377 Concurrency 380 Component Allocation 381 Operator Binding 382 Operator Scheduling 383 Moore versus Mealy High-Level State Machines 386
6.6 More on Optimizations and Tradeoffs 386 Serial versus Concurrent Computation 386 Optimizations and Tradeoffs at Higher versus Lower Levels of Design 387 Algorithm Selection 388 Power Optimization 389
6.7 Product Profile: Digital Video Player/ Recorder 393 Digital Video Overview 393 DVD--One Form of Digital Video Storage 393 MPEG-2 Video Encoding--Sending Frame Differences Using I-, P-, and B-Frames 395 Transforming to the Frequency Domain for Further Compression 396
6.8
Chapter Summary 402
6.9 Exercises 403
CHAPTER 7 Physical Implementation on ICs 413
7.1 Introduction 413
7.2 Manufactured IC Types 414 Full-Custom Integrated Circuits 414 Semicustom (Application-Specific) Integrated Circuits--ASICs 415
7.3 Off-the-Shelf Programmable IC Type--FPGA 423 Lookup Tables 424 Mapping a Circuit among Multiple Lookup Tables 426 Programmable Interconnects (Switch Matrices) 432 Configurable Logic Block 434 Overall FPGA Architecture 436
7.4 Other Off-the-Shelf IC Types 438 Off-the-Shelf Logic (SSI) IC 438 Simple Programmable Logic Device (SPLD) 441 Complex Programmable Logic Device (CPLD) 445 FPGA-to-Structured-ASIC Flows 445
7.5 IC Tradeoffs, Trends, and Comparisons 446 Tradeoffs Among IC Types 447 IC Technology Trend--Moore''s Law 448 Relative Popularity of IC Types 450 ASSPs 450 IC Types versus Processor Varieties 451 FPGAs alongside Microprocessors 452
7.6 Product Profile: Giant LED-Based Video Display with FPGAs 453
7.7
Chapter Summary 457
7.8 Exercises 457
CHAPTER 8 Programmable Processors 461
8.1 Introduction 461
8.2 Basic Architecture 462 Basic Datapath 462 Basic Control Unit 465
8.3 A Three-Instruction Programmable Processor 469 A First Instruction Set with Three Inst