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VLSI Test Principles and Architectures: Design for Testability Vital Source e-bog
Laung-Terng Wang, Cheng-Wen Wu og Xiaoqing Wen
(2006)
Elsevier Science
699,00 kr.
629,10 kr.
Leveres umiddelbart efter køb
VLSI Test Principles and Architectures
Design for Testability
Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen, Khader S. Abdel-Hafez, Wen-Ben Jone, Rohit Kapur, Brion Keller, Kuen-Jong Lee, James C. -M. Li, Mike Peng Li, Xiaowei Li, T. M. Mak, Yinghua Min, Benoit Nadeau-Dostie, Soumendu Bhattacharya, Mehrdad Nourani, Janusz Rajski, Charles Stroud, Erik H. Volkerink, Duncan M. (Hank) Walker, Shianling Wu, Nur A. Touba, Abhijit Chatterjee, Xinghao Chen, Kwang-Ting(Tim) Cheng, William Eklow, Michael S. Hsiao, Jiun-Lang Huang og Shi-Yu Huang
(2006)
Sprog: Engelsk
Elsevier Science & Technology
720,00 kr.
648,00 kr.
Print on demand. Leveringstid vil være ca 2-3 uger.
Detaljer om varen
- Vital Source searchable e-book (Fixed pages): 808 sider
- Udgiver: Elsevier Science (August 2006)
- Forfattere: Laung-Terng Wang, Cheng-Wen Wu og Xiaoqing Wen
- ISBN: 9780080474793
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
· Most up-to-date coverage of design for testability.
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
· Most up-to-date coverage of design for testability.
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
Licens varighed:
Bookshelf online: 5 år fra købsdato.
Bookshelf appen: ubegrænset dage fra købsdato.
Udgiveren oplyser at følgende begrænsninger er gældende for dette produkt:
Print: -1 sider kan printes ad gangen
Copy: højest -1 sider i alt kan kopieres (copy/paste)
Bookshelf online: 5 år fra købsdato.
Bookshelf appen: ubegrænset dage fra købsdato.
Udgiveren oplyser at følgende begrænsninger er gældende for dette produkt:
Print: -1 sider kan printes ad gangen
Copy: højest -1 sider i alt kan kopieres (copy/paste)
Detaljer om varen
- Hardback: 808 sider
- Udgiver: Elsevier Science & Technology (August 2006)
- Forfattere: Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen, Khader S. Abdel-Hafez, Wen-Ben Jone, Rohit Kapur, Brion Keller, Kuen-Jong Lee, James C. -M. Li, Mike Peng Li, Xiaowei Li, T. M. Mak, Yinghua Min, Benoit Nadeau-Dostie, Soumendu Bhattacharya, Mehrdad Nourani, Janusz Rajski, Charles Stroud, Erik H. Volkerink, Duncan M. (Hank) Walker, Shianling Wu, Nur A. Touba, Abhijit Chatterjee, Xinghao Chen, Kwang-Ting(Tim) Cheng, William Eklow, Michael S. Hsiao, Jiun-Lang Huang og Shi-Yu Huang
- ISBN: 9780123705976
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
- Most up-to-date coverage of design for testability.
- Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
- Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation
Chapter 4 - Test Generation
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age
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