Viser: RTL Hardware Design Using VHDL - Coding for Efficiency, Portability, and Scalability

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, 1. udgave
Søgbar e-bog

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability Vital Source e-bog

Pong P. Chu
(2006)
John Wiley & Sons
1.799,00 kr.
Leveres umiddelbart efter køb
RTL Hardware Design Using VHDL - Coding for Efficiency, Portability, and Scalability

RTL Hardware Design Using VHDL

Coding for Efficiency, Portability, and Scalability
Pong P. Chu
(2006)
Sprog: Engelsk
John Wiley & Sons, Incorporated
899,00 kr.
ikke på lager, Bestil nu og få den leveret
om ca. 15 hverdage

Detaljer om varen

  • 1. Udgave
  • Vital Source searchable e-book (Fixed pages)
  • Udgiver: John Wiley & Sons (April 2006)
  • ISBN: 9780471786399
The skills and guidance needed to master RTL hardware design

This book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software. Focusing on the module-level design, which is composed of functional units, routing circuit, and storage, the book illustrates the relationship between the VHDL constructs and the underlying hardware components, and shows how to develop codes that faithfully reflect the module-level design and can be synthesized into efficient gate-level implementation.

Several unique features distinguish the book:
* Coding style that shows a clear relationship between VHDL constructs and hardware components
* Conceptual diagrams that illustrate the realization of VHDL codes
* Emphasis on the code reuse
* Practical examples that demonstrate and reinforce design concepts, procedures, and techniques
* Two chapters on realizing sequential algorithms in hardware
* Two chapters on scalable and parameterized designs and coding
* One chapter covering the synchronization and interface between multiple clock domains

Although the focus of the book is RTL synthesis, it also examines the synthesis task from the perspective of the overall development process. Readers learn good design practices and guidelines to ensure that an RTL design can accommodate future simulation, verification, and testing needs, and can be easily incorporated into a larger system or reused. Discussion is independent of technology and can be applied to both ASIC and FPGA devices.

With a balanced presentation of fundamentals and practical examples, this is an excellent textbook for upper-level undergraduate or graduate courses in advanced digital logic. Engineers who need to make effective use of today's synthesis software and FPGA devices should also refer to this book.
Licens varighed:
Bookshelf online: 5 år fra købsdato.
Bookshelf appen: ubegrænset dage fra købsdato.

Udgiveren oplyser at følgende begrænsninger er gældende for dette produkt:
Print: 10 sider kan printes ad gangen
Copy: højest 2 sider i alt kan kopieres (copy/paste)

Detaljer om varen

  • Hardback: 694 sider
  • Udgiver: John Wiley & Sons, Incorporated (Maj 2006)
  • ISBN: 9780471720928
The skills and guidance needed to master RTL hardware design

This book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software. Focusing on the module-level design, which is composed of functional units, routing circuit, and storage, the book illustrates the relationship between the VHDL constructs and the underlying hardware components, and shows how to develop codes that faithfully reflect the module-level design and can be synthesized into efficient gate-level implementation.

Several unique features distinguish the book:
* Coding style that shows a clear relationship between VHDL constructs and hardware components
* Conceptual diagrams that illustrate the realization of VHDL codes
* Emphasis on the code reuse
* Practical examples that demonstrate and reinforce design concepts, procedures, and techniques
* Two chapters on realizing sequential algorithms in hardware
* Two chapters on scalable and parameterized designs and coding
* One chapter covering the synchronization and interface between multiple clock domains

Although the focus of the book is RTL synthesis, it also examines the synthesis task from the perspective of the overall development process. Readers learn good design practices and guidelines to ensure that an RTL design can accommodate future simulation, verification, and testing needs, and can be easily incorporated into a larger system or reused. Discussion is independent of technology and can be applied to both ASIC and FPGA devices.

With a balanced presentation of fundamentals and practical examples, this is an excellent textbook for upper-level undergraduate or graduate courses in advanced digital logic. Engineers who need to make effective use of today's synthesis software and FPGA devices should also refer to this book.
Preface. Acknowlegmentss.
1. Introduction to Digital System Design.
2. Overview on Hardware Description Language.
3. Basic Language Constructs of VHDL.
4. Concurrent Signal Assignment Statements of VHDL.
5. Sequential Statements of VHDL.
6. Synthesis of VHDL Code.
7. Combinational Circuit Design: Practice.
8. Sequential Circuit Design: Principle.
9. Sequential Circuit Design: Practice.
10. Finite State Machine: Princple and Practice.
11. Register Transfer Methodology: Principle.
12. Register Transfer Methodology: Practice.
13. Hierarchical Design in VHDL.
14. Parameterized Design: Principle.
15. Parameterized Design: Practice.
16. Clock and Synchronization: Principle and Practice. References. Index.

Andre har også købt

miniaturebillede af omslaget til The Designer's Guide to VHDL, 3. udgave

The Designer's Guide to VHDL

Peter J. Ashenden
Elsevier Science & Technology (2008)
792,00 kr.
Print on demand. Leveringstid vil være ca 2-3 uger.
miniaturebillede af omslaget til VLSI Test Principles and Architectures - Design for Testability

VLSI Test Principles and Architectures

Design for Testability
Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen, Khader S. Abdel-Hafez, Wen-Ben Jone, Rohit Kapur, Brion Keller, Kuen-Jong Lee, James C. -M. Li, Mike Peng Li, Xiaowei Li, T. M. Mak, Yinghua Min, Benoit Nadeau-Dostie, Soumendu Bhattacharya, Mehrdad Nourani, Janusz Rajski, Charles Stroud, Erik H. Volkerink, Duncan M. (Hank) Walker, Shianling Wu, Nur A. Touba, Abhijit Chatterjee, Xinghao Chen, Kwang-Ting(Tim) Cheng, William Eklow, Michael S. Hsiao, Jiun-Lang Huang og Shi-Yu Huang
Elsevier Science & Technology (2006)
720,00 kr. 648,00 kr.
Print on demand. Leveringstid vil være ca 2-3 uger.
miniaturebillede af omslaget til Business Model Generation - A Handbook for Visionaries, Game Changers, and Challengers

Business Model Generation

A Handbook for Visionaries, Game Changers, and Challengers
Alexander Osterwalder og Yves Pigneur
John Wiley & Sons, Limited (2010)
210,00 kr. 189,00 kr.
Bestil nu og få den leveret inden for 2-3 hverdage.
miniaturebillede af omslaget til Exploring Raspberry Pi - Interfacing to the Real World with Embedded Linux

Exploring Raspberry Pi

Interfacing to the Real World with Embedded Linux
Derek Molloy
John Wiley & Sons, Limited (2016)
299,00 kr.
ikke på lager, Bestil nu og få den leveret
om ca. 15 hverdage
miniaturebillede af omslaget til Introduction to High Performance Computing for Scientists and Engineers

Introduction to High Performance Computing for Scientists and Engineers

Georg Hager og Gerhard Wellein
CRC Press LLC (2010)
666,00 kr.
ikke på lager, Bestil nu og få den leveret
om ca. 15 hverdage

Har du brug for en faktura?

Har du brug for en faktura udstedt til din arbejdsplads, kan du med fordel oprette en konto.

 

Det tager kun et øjeblik og kontoen er klar til brug med det samme. Du skal blot bruge firmaets CVR nummer.