Hjem

About the Authors xi Foreword (professor Ray Cheung) xiii Foreword (Raghu Nambiar) xv Preface xvii Acknowledgment (Patrick Hung) xix Acknowledgment (Greg Knopf) xxi
Part I Introduction 1 1 Introduction 3
1.1 Introducing 5G and Internet of Everything 4
1.2 Edge Computing Architecture 8
1.2.1 Edge Versus Cloud Computing 10
1.2.2 Edge Design Options 11
1.2.3 Key Benefits of Edge Computing 12
1.3 Custom Computing 14
1.3.1 Introduction to Custom Computing 14
1.3.2 5G/6G Security Concerns 15
1.3.3 Custom Edge Computing Cards 17
1.4 Deployment Considerations 18
1.4.1 5G/6G Cell Architecture 19
1.4.2 5G/6G Private Network 21
1.4.3 Infrastructure Sharing 23 References 26 2 Overview of 5G and 6G 31
2.1 5G Timeline 31
2.2 5G Spectrum 32
2.3 Characteristics of 5G 34
2.4 5G New Radio 34
2.4.1 Orthogonal Frequency-Division Multiplexing 34
2.4.2 Massive MIMO 36
2.4.3 Beamforming 37
2.4.4 Multiuser MIMO 38
2.5 Data Plane and Control Plane Separation 38
2.6 5G Applications 40
2.7 Smooth Transition to 6G 42
2.8 6G Expected Timeline, Spectrum, and Characteristics 46
2.9 6G Potential Applications 48
2.10 Edge, Fog, and Cloud Computing in Relation to 5G and 6G 50
2.10.1 Edge Computing in Relation to 5G and 6G 51
2.10.2 Fog Computing in Relation to 5G and 6G 53
2.10.3 Cloud Computing in Relation to 5G and 6G 55 References 57
Part II Theory 63 3 High-Level Synthesis (HLS) 65
3.1 Why Use High-Level Synthesis? 67
3.1.1 Hardware Acceleration with High-Level Synthesis 68
3.2 Common HLS Languages and Platforms 69
3.2.1 Compute Unified Device Architecture (CUDA) 70
3.2.1.1 CUDA and HLS for Hardware Acceleration 70
3.2.1.2 Advantage of Using CUDA and HLS for Hardware Acceleration 71
3.2.2 OpenCL 72
3.2.2.1 OpenCL and HLS for Hardware Acceleration 73
3.2.2.2 Advantages of Using OpenCL with HLS Tools for Hardware Acceleration 74
3.2.3 Maxeler MaxJ 75
3.2.3.1 Using Maxeler MaxJ with HLS for Hardware Acceleration 76
3.2.3.2 Advantages of Using Maxeler MaxJ with HLS for Hardware Acceleration 77
3.3 Limitations and Challenges of HLS 79
3.4 Using HLS in 5G Edge Computing 80
3.4.1 User (Data) Plane Acceleration 81
3.4.2 Control Plane Acceleration 82
3.4.3 Advantages of Using HLS for User Plane and Control Plane Acceleration 83 References 85 4 Coding Design 89
4.1 Overview 89
4.2 Error Correction Codes (ECCs) 90
4.2.1 Turbo, Low-Density Parity-Check, and Polar Codes 92
4.2.1.1 Turbo Codes 93
4.2.1.2 LDPC Codes 94
4.2.1.3 Polar Codes 97
4.3 Security Codes 98
4.3.1 Public Key Infrastructure 99
4.3.2 Symmetric and Asymmetric Cryptography Concepts 100
4.3.2.1 Symmetric Key Cryptography 100
4.3.2.2 Asymmetric Key Cryptography 101
4.3.3 Existing Algorithms and Standards 103
4.3.3.1 Advanced Encryption Standard 103
4.3.3.2 RSA Algorithm 103
4.3.3.3 Elliptic Curve Cryptography 104
4.4 Emerging 5G Security Design Acceleration 105
4.4.1 Blockchain 105
4.4.2 Lightweight Encryption Algorithms 108
4.4.2.1 SIMON and SPECK Algorithms 108
4.4.2.2 PRESENT Algorithm 110
4.4.2.3 GIFT Algorithm 112
4.4.3 Network Codes 113
4.4.4 Post-Quantum Cryptography 115
4.4.5 Homomorphic Encryption 116
4.4.6 Zero-Knowledge Proof 118 References 120
Part III Architecture 125 5 Hardware Architecture 127
5.1 Development Timeline 127
5.2 Operating Spectrum 128
5.3 Core Requirements 133
5.4 New Radio Access Technology 135
5.4.1 Orthogonal Frequency-Division Multiplexing 135
5.4.2 Massive MIMO (Multiple-Input Multiple-Output) 137
5.4.3 Beamforming 137
5.4.4 Multiuser MIMO 138
5.5 Network Architecture 138
5.5.1 Next Generation Radio Access Network 139
5.5.2 5G Core 140
5.5.2.1 Control and User Plane Separation (CUPS) 140
5.5.2.2 Service-Based Architecture (SBA) 140
5.6 Performance Improvement 142
5.6.1 Computing and Network Convergence 142
5.6.2 Related Works 144
5.6.3 Smart_xPU Design Methodology 148
5.6.3.1 Data Flow Optimization 148
5.6.3.2 Distributed System Optimization 151
5.6.3.3 Core Microarchitecture Optimization 154
5.6.3.4 Software/Hardware Interface Optimization 156
5.6.3.5 Analyzing the Smart_xPU Architecture 159
5.6.4 Summary of the Smart_xPU Architecture 160 References 162 6 Software Architecture 167
6.1 End-to-End Example of 5G System 167
6.1.1 High-Level Description 167
6.1.1.1 5G Radio Access Network 168
6.1.1.2 Edge 169
6.1.1.3 5G Core 169
6.1.1.4 Application and Services 171
6.1.2 Interfaces 171
6.1.2.1 N1: Between 5G Core and User Equipment 171
6.1.2.2 N2: Between 5G Core and Base Station 171
6.1.2.3 N3: Between RAN and User Plane Function 172
6.1.2.4 Other Interfaces Include the Following 172
6.2 Network Slicing Architecture, Software-Defined Network, and Network Function Virtualization 173
6.2.1 Network Slicing Architecture 173
6.2.1.1 Software-Defined Network (SDN) 174
6.2.1.2 Network Function Virtualization (NFV) 176
6.3 Software Acceleration 178
6.3.1 User Space Approach 178
6.3.1.1 Data Plane Development Kit (DPDK) 178
6.3.2 Other Approaches 183
6.3.2.1 Remote Direct Memory Access (RDMA) 183
6.3.2.2 Compute Express Link (CXL) 186
6.3.2.3 Data Processing Unit (DPU) 188 References 190
Part IV Applications 193 7 Killer Applications 195
7.1 Metaverse and Its Trends 195
7.2 Technologies Behind Metaverse 197
7.2.1 Artificial Intelligence 197
7.2.1.1 AI-Based Non-player Character 199
7.2.1.2 Sensory Capabilities with AI 199
7.2.2 Blockchain 200
7.2.2.1 Power Consumption 201
7.2.3 AR and VR 202
7.2.4 Internet of Things 203
7.3 Applications of Metaverse 204
7.3.1 Gaming 204
7.3.2 Education 205
7.3.3 Commerce 206
7.3.4 Social Networking 207
7.3.5 Healthcare 208
7.3.6 Industrial Use 210
7.3.7 Entertainment 211
7.4 Accelerating Killer Apps 213
7.4.1 Edge Computing 214
7.4.2 Acceleration by Specialized Hardware 215 References 216 8 From Concept to Production 225
8.1 System Design Process 225
8.2 Some Examples 230
8.3 Standards Compliance 233
8.4 Other Design Metrics 234
8.5 Summary 237 References 237
Part V Future Roadmap 241 9 The Road Ahead 243
9.1 Spatial Computing and Networking 245
9.2 Supporting 5G/6G Spatial Computing and Networking 246
9.3 Migrating to 6G 248
9.3.1 Cutting Edge 6G Research 249
9.4 Enabling Technologies for 5G and Beyond 251
9.4.1 Processing-in-Memory Architecture 251
9.4.2 New Packaging Architecture 253
9.4.3 New Memory Architecture 255
9.4.4 Artificial Intelligence-Driven Architectures 257
9.5 Some Final Thoughts 259 References 259 Index 263